Robust post-gate spacer processing and device

ABSTRACT

A methodology for robust post-gate spacer processing that exhibits reduced variability and marginalities, and the resulting device are disclosed. Embodiments may include forming an oxide layer over a gate stack, forming a nitride layer over the oxide layer, partially removing the nitride layer to expose a portion of the oxide layer, forming a protective nitride layer directly over the partially exposed oxide layer and a remaining portion of the nitride layer, removing the protective nitride layer from the gate stack, and at least partially removing the remaining portion of the nitride layer.

TECHNICAL FIELD

The present disclosure relates to the fabrication of semiconductordevices having variable gate lengths. The present disclosureparticularly relates to post-gate, pre-silicidation spacer processing atgate pitch values for the 32 nanometer (nm) technology node and beyond.

BACKGROUND

Modern integrated circuits (ICs) utilize several different polysilicon(“poly”) pitch values depending on a desired gate length for aparticular device on the IC. However, continuously scaled pitch valuesminimize the space available for implants, stress memorizationtechniques, silicidation, dual stress liners, and contacts. Asdimensions shrink, the process margin in each individual process stepand tolerance for process variability decreases.

Also, after spacers are formed, a silicide block mask, or resistorprotection layer, is required to protect the poly and diffusionresistors from silicide formation. To protect the underlying layers whenthe resistor protection layer is removed (from places in which asilicide is to be formed), an oxide etch stop layer is formed under theprotection layer. The etch stop layer must then be removed to expose thesilicon source and drain regions for silicidation. In addition, a spacerpull back process (i.e., partial removal of the outermost spacers) isrequired prior to contact integration to increase the space for thesource and drain contacts. However, the spacer etch erodes the silicide,which increases contact resistance, which in turn degrades deviceperformance.

A need therefore exists for methodology enabling a more robust andcost-efficient post-gate spacer processing while allowing cost-efficientgate pitch scaling.

SUMMARY

An aspect of the present disclosure is skipping an oxide linerdeposition under a silicide block mask and removal thereof duringpost-gate processing.

Another aspect of the present disclosure is depositing a nitrideresistor protection layer directly over a partially exposed oxide layerand combining a spacer pull back process with etching of the resistorprotection layer prior to silicidation.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure, some technical effects may beachieved in part by a method including: forming an oxide layer over agate stack, forming a nitride layer over the oxide layer, partiallyremoving the nitride layer to expose a portion of the oxide layer,forming a protective nitride layer directly over the partially exposedoxide layer and a remaining portion of the nitride layer, and removingthe protective nitride layer from the gate stack and at least partiallyremoving the remaining portion of the nitride layer.

Aspects of the present disclosure include the gate stack including agate electrode, a nitride formed on sidewalls of the gate electrode, andoxide formed on the nitride. Further aspects include partially removingthe nitride layer by reactive ion etching (RIE) horizontal surfaces ofthe nitride layer. Additional aspects include partially removing thenitride layer to expose the oxide layer at a top surface of the gatestack. Further aspects include partially removing the remaining portionof the nitride layer to expose the oxide layer at top and upper sidewallsurfaces of the gate stack. Additional aspects include removing exposedportions of the oxide layer to expose top and upper sidewall surfaces ofa gate electrode, and forming a gate silicide at exposed portions of thegate electrode. Further aspects include forming the nitride layerdirectly on the oxide layer. Additional aspects include the gate stackincluding a high-K metal gate (HKMG). Further aspects include formingthe protective nitride layer to a thickness of 100 to 300 angstroms (Å).

Another aspect of the present disclosure is a method including formingan oxide layer over a gate stack, forming a nitride layer over the oxidelayer, partially removing the nitride layer to expose a portion of theoxide layer, forming a protective nitride layer directly over thepartially exposed oxide layer and a remaining portion of the nitridelayer, and removing the protective nitride layer from the gate stack andat least partially removing the remaining portion of the nitride layer,the partial removal of the nitride layer exposing the oxide layer at atop surface of the gate stack, and at least partially removing theremaining portion of the nitride layer to expose the oxide layer at topand upper sidewall surfaces of the gate stack. Additional aspectsinclude the gate stack including a gate electrode, a nitride formed onsidewalls of the gate electrode, and oxide formed on the nitride.Further aspects include partially removing the nitride layer by RIEhorizontal surfaces of the nitride layer. Additional aspects includeremoving exposed portions of the oxide layer to expose top and uppersidewall surfaces of a gate electrode and forming a gate silicide atexposed portions of the gate electrode. Further aspects include formingthe nitride layer directly on the oxide layer. Additional aspectsinclude the gate stack including a HKMG. Further aspects include formingthe protective nitride layer to a thickness of 100 to 300 Å.

Aspects include a method comprising: forming an oxide layer over a gatestack, a source region, and drain region, forming a nitride layer overthe oxide layer, partially removing the nitride layer to expose aportion of the oxide layer at a top surface of the gate stack and thesource and drain regions, performing a deep implantation at the sourceand drain regions, forming a protective nitride layer directly over theexposed portion of the oxide layer, the source and drain regions, and aremaining portion of the nitride layer, removing the protective nitridelayer from the gate stack and the source and drain regions, and at leastpartially removing the remaining portion of the nitride layer, to exposea portion of the oxide layer at top and upper sidewall surfaces of thegate stack and over the source and drain regions, removing the exposedportions of the oxide layer to expose top and upper sidewall surfaces ofa gate electrode and the source and drain regions, and forming asilicide on the gate electrode and the source and drain regions.Additional aspects include the gate stack including a HKMG, a nitrideformed on sidewalls of the HKMG, and oxide formed on the nitride.Further aspects include forming the nitride layer directly on the oxidelayer and partially removing the nitride layer by RIE horizontalsurfaces of the nitride layer. Additional aspects include forming theprotective nitride layer to a thickness of 100 to 300 Å.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIGS. 1A through 1G schematically illustrate a conventional post-gatespacer process; and

FIGS. 2A through 2G schematically illustrate a robust, post-gate spacerprocess, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments. Inaddition, unless otherwise indicated, all numbers expressing quantities,ratios, and numerical properties of ingredients, reaction conditions,and so forth used in the specification and claims are to be understoodas being modified in all instances by the term “about.”

FIGS. 1A through 1F schematically illustrate a conventional post-gateprocessing, including spacer and resistor protection processes from afirst spacer process until silicide formation. FIG. 1A illustratesformation of a first, post-gate, spacer (e.g., SP0). By way of example,gate 101 (e.g., a complex HKMG, gate stack formed by a gate firstprocess) includes polysilicon 103 and gate oxide 105 formed on substrate107. First spacers (SP0) 109 may include nitride liner 111 and oxide 113formed on sidewalls of gate 101. Next, oxide liner layer 115 (forexample of silicon dioxide (SiO₂)) and nitride layer 117 aresequentially deposited over the gate stack and substrate (FIG. 1B).Nitride layer 117 is then etched to form second spacers (SP1), therebyexposing portion 119 of oxide liner layer 115 on top of gate 101 (FIG.1C). As shown, the etching removes the portion of nitride layer 117 atthe top of polysilicon 103 and at source and drain regions 121 ofsubstrate 107.

Following source and drain region implantations (not shown forillustrative convenience), an etch stop oxide liner 123 and nitrideresistor protection layer 125 are sequentially deposited (FIG. 1D). Etchstop oxide liner 123 is formed over portion 127 of oxide liner layer 115that was previously exposed by the etching process. Next, nitrideresistor protection layer 125 is selectively etched to expose etch stopoxide liner 123 (FIG. 1E). The selective etching only removes nitrideresistor protection layer 125 at the location of the gate. Accordingly,nitride resistor protection layer 125 remains elsewhere, as on p-dopedpolysilicon and active region well resistors (not shown for illustrativeconvenience) to protect them during silicidation. Etch stop oxide liner123 acts as an etch stop during the nitride etching, protecting oxideliner layer 115.

Next, etch stop oxide liner 123 is removed during a pre-silicidecleaning step to expose the top of polysilicon 103 and source and drainregions 121 (FIG. 1F). Residual materials will also be removed to readya clean surface for a silicidation process. The pre-silicide cleaningprocess may pull back oxide liner layer 115 and nitride layer 117 (i.e.,spacers SP1). Finally, silicide 129 (for example cobalt silicide (CoSi),nickel silicide (NiSi), or titanium silicide (TiSi) is created onpolysilicon 103 and the source and drain regions (FIG. 1G). As shown,nitride layer 117 remains after cleaning, thus requiring at leastpartial removal/shaping by an RIE spacer etch prior to contactintegration. However, in addition to removing the nitride, RIE alsoattacks silicide 129 over source and drain regions 121. Degradation ofthe source/drain region silicide 129 increases serial resistance and,therefore, degrades device performance.

The present disclosure addresses and solves the current problem ofincreased process steps, high serial resistance in PMOS devices and highcontact resistance, attendant upon SP1 spacer shaper etching. Inaccordance with embodiments of the present disclosure, a post-gate oxideliner deposition step is skipped allowing SP1 to be pulled back prior tosilicidation, thereby eliminating the spacer shaper steppost-silicidation.

Methodology in accordance with embodiments of the present disclosureincludes forming an oxide layer over a gate stack, forming a nitridelayer over the oxide layer, partially removing the nitride layer toexpose a portion of the oxide layer, forming a protective nitride layerdirectly over the partially exposed oxide layer and a remaining portionof the nitride layer, removing the protective nitride layer from thegate stack, and at least partially removing the remaining portion of thenitride layer.

Still other aspects, features, and technical effects will be readilyapparent to those skilled in this art from the following detaileddescription, wherein preferred embodiments are shown and described,simply by way of illustration of the best mode contemplated. Thedisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects. Accordingly, the drawings and description are to be regardedas illustrative in nature, and not as restrictive.

FIGS. 2A through 2F schematically illustrate a post-gate processing,according to an exemplary embodiment of the present disclosure. FIG. 2Aillustrates formation of a first, post-gate, spacer (SP0). Gate 201 mayinclude polysilicon 203 and gate oxide 205 formed on substrate 207. Asshown, SP0 spacer 209 may include nitride liner 211 and oxide 213 formedon sidewalls of gate 201. Adverting to FIG. 2B, oxide liner 215 andnitride 217 are deposited. By way of example, oxide liner 215 may beformed of SiO₂ and nitride 217 may be formed of silicon nitride (SiN).Adverting to FIG. 2C, nitride 217 is etched to form second spacers(SP1), exposing portion 219 of oxide liner 215 on top of an uppersurface of polysilicon 203. As shown, the etching removes the portion ofnitride 217 at the top of polysilicon 203 and at source and drainregions 221. By way of example, an anisotropic etch process (e.g., RIE)may be used in order to limit the etching to horizontal portions ofnitride 217.

Following deep source and drain region implantations (not shown forillustrative convenience), protective nitride layer 223 is formed overthe gate stack and substrate (FIG. 2D). In contrast to conventionalpost-gate processing, an etch stop oxide layer (e.g., oxide liner layer115 in FIG. 1D) is not deposited. Instead, protective nitride layer 223is deposited to directly contact upper surface 225 of oxide liner 215that was exposed by the anisotropic etch. Also, protective nitride layer223 is formed directly over nitride 217 of spacers SP1. Protectivenitride layer 223 may be a SiN layer that protects p-doped polysiliconand active layer well resistors (not shown for illustrative convenience)from silicidation.

Next, protective nitride layer 223 is etched to expose horizontalportion 227 of oxide liner 215 (over gate 201) and portions over sourceand drain regions 221 (FIG. 2E). As shown, the etching also partiallyremoves nitride 217 of spacers SP1, exposing an upper portion 229 of thevertical surfaces of oxide liner 215. Nitride 217 may be completelyremoved by the etching process depending on the process properties. Asdiscussed previously in relation to FIG. 1E, protective nitride layer223 has been etched to expose gate and source and drain regions 221 forsilicidation. However, protective nitride layer 223 remains elsewhere onp-doped polysilicon and active region well resistors (not shown forillustrative convenience) to protect them during the silicidation.

Adverting to FIG. 2F, a pre-silicide cleaning step is performed. Thecleaning provides a clean surface for silicidation by removing exposedportions of oxide liner 215 and any residual materials. By way ofexample, the cleaning process may be a hydrochloric acid (HCl) pre-cleanprocess that interacts with and removes SiO₂ of oxide liner 215. Asillustrated, the pre-cleaning process has a substantial and significantpull back effect. For example, the pre-cleaning pulls back nitride liner211, oxide 213 of spacers SP0, oxide liner 215, and nitride 217 ofspacers SP1. As a result, polysilicon 203 is more open and exposedcompared to the conventional process. The greater exposure aidssilicidation. The increased silicidation in turn results in a loweralternating current-effective resistance (ACReff), which improves ringoscillator/alternating current (RO/AC) performance.

FIG. 2G illustrates a post-silicidation step where silicide 231 iscreated on polysilicon 203 and on source and drain regions 221. By wayof example, the silicide may include a CoSi, NiSi, TiSi, in addition toother possible silicides. In contrast to a conventional post-gateprocessing, nitride 217 is greatly reduced and, therefore, a post-spacershaper etch is not required prior to contact integration. As a result,the source and drain regions are not damaged because there is nosilicide erosion. Thus, a lower serial resistance and improved deviceperformance is obtained compared to conventional post-gate processing.In addition, the overall process cost is lowered because the oxide etchstop layer and removal thereof and the spacer shaper etch step are notrequired. Furthermore, a fully silicided gate electrode (FUSI) isachieved, which results in lower ACReff. This in turn improves RO/ACperformance. It is contemplated that performance will especially beimproved on PFET devices because no silicide erosion occurs.

The embodiments of the present disclosure can achieve several technicaleffects, including an improved device performance, and robust, costefficient, post-gate processing. The present disclosure enjoysindustrial applicability associated with the designing and manufacturingof any of various types of highly integrated semiconductor devices usedin microprocessors, smart phones, mobile phones, cellular handsets,set-top boxes, DVD recorders and players, automotive navigation,printers and peripherals, networking and telecom equipment, gamingsystems, and digital cameras.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

1. A method comprising: forming an oxide layer over a gate stack, thegate stack having a bottom surface on a substrate and a top surfaceopposite the bottom surface; forming a nitride layer over the oxidelayer; partially removing the nitride layer to expose a portion of theoxide layer, wherein partially removing the nitride layer exposes theoxide layer directly above the top surface of the gate stack; forming aprotective nitride layer directly over the partially exposed oxide layerand a remaining portion of the nitride layer; and removing theprotective nitride layer from the gate stack and at least partiallyremoving the remaining portion of the nitride layer.
 2. The method ofclaim 1, wherein the gate stack comprises: a gate electrode; nitrideformed on sidewalls of the gate electrode; and oxide formed on thenitride.
 3. The method of claim 1, comprising partially removing thenitride layer by reactive ion etching (RIE) horizontal surfaces of thenitride layer.
 4. (canceled)
 5. The method of claim 1, wherein partiallyremoving the remaining portion of the nitride layer exposes the oxidelayer at upper sidewall surfaces of the gate stack.
 6. The method ofclaim 5, further comprising: removing exposed portions of the oxidelayer to expose top and upper sidewall surfaces of a gate electrode; andforming a gate silicide at exposed portions of the gate electrode. 7.The method of claim 1, comprising forming the nitride layer directly onthe oxide layer.
 8. The method of claim 1, wherein the gate stackcomprises a high-K metal gate (HKMG).
 9. The method of claim 1,comprising forming the protective nitride layer to a thickness of 100 to300 angstroms (Å).
 10. A method comprising: forming an oxide layer overa gate stack, the gate stack having a bottom surface on a substrate anda top surface opposite the bottom surface; forming a nitride layer overthe oxide layer; partially removing the nitride layer to expose aportion of the oxide layer directly above the top surface of the gatestack; forming a protective nitride layer directly over the partiallyexposed oxide layer and a remaining portion of the nitride layer; andremoving the protective nitride layer from the gate stack and at leastpartially removing the remaining portion of the nitride layer, whereinpartially removing the nitride layer exposes the oxide layer at the topsurface of the gate stack, and wherein at least partially removing theremaining portion of the nitride layer exposes the oxide layer at thetop surface and upper sidewall surfaces of the gate stack.
 11. Themethod of claim 10, wherein the gate stack comprises: a gate electrode;nitride formed on sidewalls of the gate electrode; and oxide formed onthe nitride.
 12. The method of claim 10, comprising partially removingthe nitride layer by reactive ion etching (RIE) horizontal surfaces ofthe nitride layer.
 13. The method of claim 10, further comprising:removing exposed portions of the oxide layer to expose top and uppersidewall surfaces of a gate electrode; and forming a gate silicide atexposed portions of the gate electrode.
 14. The method of claim 10,comprising forming the nitride layer directly on the oxide layer. 15.The method of claim 10, wherein the gate stack comprises a high-K metalgate (HKMG).
 16. The method of claim 10, comprising forming theprotective nitride layer to a thickness of 100 to 300 angstroms (Å). 17.A method comprising: forming an oxide layer over a gate stack, a sourceregion, and a drain region, the gate stack having a bottom surface on asubstrate and a top surface opposite the bottom surface; forming anitride layer over the oxide layer; partially removing the nitride layerto expose a portion of the oxide layer directly above the top surface ofthe gate stack and the source and drain regions; performing a deepimplantation at the source and drain regions; forming a protectivenitride layer directly over the exposed portion of the oxide layer, thesource and drain regions, and a remaining portion of the nitride layer;removing the protective nitride layer from the gate stack and the sourceand drain regions, and at least partially removing the remaining portionof the nitride layer, to expose a portion of the oxide layer at the topsurface and upper sidewall surfaces of the gate stack and over thesource and drain regions; removing the exposed portions of the oxidelayer to expose top and upper sidewall surfaces of a gate electrode andthe source and drain regions; and forming a silicide on the gateelectrode and the source and drain regions.
 18. The method of claim 17,wherein the gate stack comprises: a high-K metal gate (HKMG); nitrideformed on sidewalls of the HKMG; and oxide formed on the nitride. 19.The method of claim 17, comprising forming the nitride layer directly onthe oxide layer and partially removing the nitride layer by reactive ionetching (RIE) horizontal surfaces of the nitride layer.
 20. The methodof claim 17, comprising forming the protective nitride layer to athickness of 100 to 300 angstroms (Å).